Chiplet

It is assumed in many quarters that the world of computing will never be the same with the coming of Chiplet. The name indicates that it is basically a smaller chip. Multiple and interconnected chiplets create a large integrated circuit, a vital part of packaging architecture, with well-defined subset of functionalities. Chiplet is poised to have much impact on the tech and business worlds simply by doing away with monolithic circuits. Semiconductor giants like AMD (Advanced Micro Devices), Intel and TSMC are using chiplet-based processors with much competitiveness among themselves and for ensuring competitive edge in business and consumer markets.

AMD's latest EPYC processors feature up to eight chiplets, each with up to eight cores, and 32 megabytes of level 3 (L3) cache for a total of 64 cores, 128 threads, and 256 megabytes L3 cache. Its first generation EPYC processor hosted four chiplets. Intel could not remain far behind in adopting the chiplet model and it has announced the introduction of compute tiles with full access to all resources, including cache, memory, and input/output (I/O) functionality on all tiles. The sophisticated core, Intel claims, is also optimized for Artificial Intelligence (AI) workloads. And if AI is there machine learning cannot be far behind.

Very high-performance expectation is the driving force behind the production and marketing of chiplets. It is not just improvement in performance but attainment of outstanding performance is what matters most. The next-generation CPUs produced by these two tech giants are foregrounded as ‘superb performers’. Such degree of performance is modularized with the goal of reducing product development times and costs and customer-friendly mix and match mode of interconnections. But the chiplet ecosystem is still being constructed and during this stage it faces some decisive challenges. In other words, there is no overnight expansion of the chiplet model; nor will there be ready acceptance of chiplet technology by all companies in near future. There are a number of observers who point out that monolithic die is not going to evaporate at all as it remains a lowest cost option. It is also argued that those companies which cannot afford to go for high-performance will desist from adopting the chiplet model.

First and foremost, many companies do not have the technological wherewithal to receive and adopt chiplet technology. Second, there is still a dearth of third party die-to-die interconnect technology which is yet to acquire a mature form. Third, design support in this sphere is also gradually developing and much remains to be done. One major issue in this case remains the possibility of reuse of chiplets, which itself is a tedious and time consuming task. Fourth, it is not that easy to find vendors with the right IP and manufacturing capacities, both of which are important in not only linking SOCs and chiplets but also in validating the IP on silicon for performance validation. Fifth, there is the problem of interoperability of chiplets produced by different companies and this remains a decisive challenge to encounter. Not the least, despite its close linkage with the business world the chiplet-related supply chain is still underdeveloped and is often found to be lacking the level of sophistication that is required to keep pace with such technology development. With so many challenges and none of them being simple there is a chance that a number of customers may have a second thought in embracing the chiplet model and may look for a more advanced traditional approach, say, in chip scaling.

There is no denying that the chiplet revolution is marked with a lot of challenges and constraints. But that does not diminish the importance of chiplets which come with novel solutions and a wide range of possibilities. One may conclude that the business world being composed of companies of varying resources and capabilities, there should be a choice to exercise on the exact kind of technology, chiplet or otherwise.