ARYABHAT-1 will allow artificial intelligence and machine learning apps to perform much better and faster
Artificial Intelligence and Machine Learning have been niche subjects with very limited implementations in mainstreaming computing and usage. ML is a subfield of AI, which enables machines to learn from past data or experiences without being explicitly programmed. The Indian Institute of Science (IISc) has developed a design framework to build next-generation analog computing chipsets that could be faster and require less power than the digital chips found in most electronic devices. It has been designed by Pratik Kumar, who is a Ph.D. student at IISc.
With this novel design framework, the IISc research team has built a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable Technology And Bias-scalable Hardware for AI Tasks), that will allow AI and ML apps to perform much better and faster. This type of chipset could be especially helpful for artificial intelligence-based applications such as object or speech recognition think Alexa or Siri. They are useful in operations that require massive parallel computing at high speeds. Most electronic devices, particularly those that involve computing, use digital chips because the design process is simple and scalable.
ARYABHAT-1 for AI and ML tasks:
Chetak Singh Thakur, an Assistant Professor at the Department of Electronic Systems Engineering (DESE), IISc states that The advantage of analog is huge. You will get orders of magnitude improvement in power and size, whose lab is leading the efforts to develop the analog chipset. In applications that do not require precise calculations, analog computing has the potential to outperform digital computing as the former is more energy-efficient.
The IISc researchers say that different machine learning architectures can be programmed on ARYABHAT-1 and like most digital processors, it can operate robustly across a wide range of temperatures. However, there are several technical hurdles to overcome while designing analog chips. Unlike digital chips, testing and co-design analog processors are difficult. And another challenge is trading off precision and speed with power and area is not easy when it comes to analog design. To overcome these challenges, the team has designed a novel framework that allows the development of analog processors which scale just like digital processors.
They add that the architecture is also “bias-scalable” that is, its performance remains the same when the operating conditions like voltage or current are modified. the theory of analog bias-scalable computing being manifested in reality and for practical applications. This means that the same chipset can be configured for either ultra-energy-efficient IoT applications or for high-speed tasks like object detection. The researchers have outlined their findings in two pre-print studies that are currently under peer review. They have also filed patents and are planning to work with industry partners to commercialize the technology.